Electronic equipment such as telephones, radios, televisions, games and computers comprise largely of semiconductor components. The low standby power demands of CMOS makes it especially suited for many of today's applications. Some of these semiconductor components comprise both low voltage transistors optimized for in chip processing referred to as core devices (core nMOS and core pMOS) and higher voltage devices referred to as I/O devices (I/O nMOS and I/O pMOS) optimized for between chip processing usually located near the periphery of the structure. A CMOS transistor includes source and drain regions formed in the face of the semiconductor layer with a gate insulatively disposed adjacent the face of the semiconductor layer and between the source and drain regions. The channel region between the source and drain is of opposite conductivity type to the source and drain. Pocket implants may also be formed generally self-aligned to the gate and adjacent to the source and/or drain regions. Pocket implants are of dopants that are of the same type as the channel and of opposite type as that in the source/drain. See Chatterjee et al. U.S. Pat. No. 6,287,920 B1 and Nandakumar et al. U.S. Pat. No. 6,228,725 B1 incorporated herein by reference. The high voltage MOS devices have a thicker gate oxide (for gate oxide integrity and time dependent dielectric breakdown (TDDB)) and have longer length and graded LDD (Lightly Doped Drain) implant (for channel hot carrier (CHC) reliability). The lower voltage devices use pocket implants to control the short channel threshold voltage roll off and not typically used in high voltage or I/O devices because of the longer length since control is easier and the threshold voltage will be raised (which produces undesirable CHC). See application Ser. No. 09/589,953 filed Jun. 8, 2000 of Amitava Chatterjee et al. entitled “Method to Partially or Completely suppress Pocket Implant in Selective Circuit Elements With No Additional Mask in a CMOS Flow Where Separate Masking Steps are Used for the Drain Extension Implants for the Low Voltage and High Voltage Transistors.” This application is incorporated herein by reference. Also see article of A. Chatterjee et a. in Symposium of VLSI Technology pp. 147–148, in 1999 entitled “Transistor Design Issues in Integrating Analog Functions with High Performance Digital CMOS.”
A typical CMOS flow includes the following steps:                1. Shallow Trench Isolation.        2. Pattern and implant p-well implants.        3. Pattern and implant n-well implants.        4. Implant damage anneal.        5. Gate Module for split gate.        6. Drain extension patterns and implants as follows not necessarily in order: pattern and implant drain extensions and pocket for core nMOS; pattern and implant drain extensions and pocket for pMOS; pattern and implant drain extensions and pocket for I/O nMOS; and pattern and implant drain extensions and pocket for I/O pMOS.        7. Sidewall deposit and etch.        8. Source/drain pattern and implant for nMOS.        9. Source/drain pattern and implant for pMOS.        10. Silicide module.        11. Contact module.        12. Dual Damascene Cu metalization module.        13. Protective Overcoat.        
Bipolar transistor devices are characterized by higher switching speeds and larger output currents than MOS, but are not formed with the circuit density of MOS circuits and bipolar devices do not give the much lower standby power of CMOS circuits. It is desired for many reasons to integrate bipolar and MOS devices. In one preferred application the bipolar transistor is used to build “bandgap reference” circuits. The exponential relationship between current and voltage of the bipolar transistor is utilized to generate a reference voltage. There have been many articles and patents in this area of this technology. See for, example Vittoz, IEEE JSSC June 1983, page 273 and discussion in Holman and Connelly, IEEE JSSC June 1995, p710. There are also many patents such as U.S. Pat. No. 4,669,177 of D'Arrigo et al. and U.S. Pat. No. 6,075,272 of Prall et al. There is a desire to form bipolar junction transistors in a CMOS flow at no added cost.
There are lateral bipolar junction transistors formed in MOSFET devices with reference to p-substrate and n-well. A parasitic vertical pnp with n-well base with p+ source/drain emitter, n-well base and p substrate collector has been produced and is illustrated in FIG. 1. The base region below the emitter contact is an n-well region. The base contact is formed by an n-well region and by the implants used in the nMOS source/drain regions. One may choose to include or omit the implants done in the core nMOS during the core nMOS Lightly Doped Drain (LDD) extender implants and pocket implants steps. Likewise one may choose to include or omit the implants used in any other nMOS in the CMOS flow such as the I/O nMOS. The emitter contact is formed by the implants used in the pMOS source/drain regions. One may choose to include or omit the implants done in the core pMOS during the core pMOS LDD extender implants and pocket implant steps. For the pMOS LDD extender implant BF2 (boron and fluorine) may be used and for the pocket phosphorous implant may be used. Likewise one may choose to include or omit the implants used in any other pMOS in the CMOS flow such as the I/O pMOS. The collector region below the base is the p-substrate and the p-well region along with the implants used in the pMOS source/drain regions form the collector contact. The active regions may or may not be silicided or part of the regions may be silicided depending on the options available in the CMOS flow. Note that the pocket implants are always the opposite type as the source/drain; namely, for a pMOS the pocket is donor type while the LDD extender and the source/drain implants are acceptor type.
Another prior art bipolar device is a parasitic lateral pnp formed with p+ source/drain emitter and collector with n-well base as illustrated in FIG. 2. The emitter and collector contacts are formed by the implants used in the pMOS source/drain regions. One may choose to include or omit the implants done in the core pMOS during the core pMOS LDD extender and pocket implant steps. Likewise one may choose to include or omit the implants used in any other pMOS in the CMOS flow such as the I/O pMOS. The vertical pnp as described in FIG. 1 is present here but is considered as a parasitic device. The base region below the emitter and collector contacts is an n-well region. The base region going laterally from the emitter to the collector has the n-well and the pocket implants in the cases where the emitter and collector includes the core pMOS LDD extender and pocket implants (indicated by dashed lines). Note that the pocket implants are always the opposite conductivity type as the source/drain; namely, for a pMOS the pocket is donor type while the LDD extender and source/drain are acceptor type. The base contact is formed by an n-well region and by the implants used in the nMOS source/drain regions. One may choose to include or omit the implants done in the core nMOS during the core nMOS LDD extender and pocket implant steps. Likewise one may choose to include or omit the implants used in any other nMOS in the CMOS flow such as the I/O nMOS. The active regions may or may not be silicided or part of the regions may be silicided depending on the options available in the CMOS flow. The polysilicon may be p-type or n-type depending on the CMOS flow and how the poly is implanted. The purpose of the polysilicon is to block suicide shorting the emitter to base and to collector. In cases where the flow has a silicide block pattern then the suicide block layer such as silicon nitride can be used. The polysilicon gate is typically connected electrically to the emitter.
A third prior art bipolar device is a vertical pnp with compensated well emitter, n-well base and p-substrate collector. The base region below the emitter contact is a “compensated well” region. In a dual well CMOS flow the n-well regions are normally implanted with one set of implants and the p-well region is implanted with a second set of implants. A “compensated well” region means a region where all the implants present normally in the n-well as well as all the implants done normally in the p-well regions are superimposed. In one such process the configuration is like that in FIG. 3. The base contact is formed by an n-well region and by the implants used in the nMOS source/drain regions. One may choose to include or omit the implants done in the core nMOS during the core nMOS LDD extender implant and pocket implant steps. Likewise, one may choose to include or omit the implants used in any other nMOS in the CMOS flow such as the I/O nMOS. The emitter contact is formed by the implants used in the pMOS source/drain regions. One may choose to include or omit the implants done in the core pMOS during the core pMOS LDD extender and pocket implants steps. Likewise one may choose to include or omit the implants used in any other pMOS in the CMOS flow such as the I/O pMOS. The collector region below the base is the p-substrate and the high-energy retrograde boron implant that, in this case, is deeper than the corresponding phosphorus implant. The p-well region along with the implants used in the pMOS source/drain regions from the collector contact. The active regions may or may not be silicided or part of the regions may be silicided depending on the options available in the CMOS flow. Note that the pocket implants are always the opposite type as the source/drain; namely, for a pMOS the pocket is donor type while the LDD and source/drain are acceptor type.
A fourth is a triple well that allows several other options but this adds cost by adding more pattern and implant steps to the flow. The emitter contact is formed by the implants used in the nMOS source/drain regions. One may choose to include or omit the implants done in the core nMOS during the core nMOS LDD and pocket implant steps. Likewise one may choose to include or omit the implants used in any other nMOS in the CMOS flow such as the I/O nMOS. The base region below the emitter contact is a p-well region. The base contact is formed by the implants used in the pMOS source/drain regions. The collector region is a deep n-well region formed, for example, by a high energy implant. The collector contact is formed by an n-well region and by the implants used in the nMOS source/drain regions. The active regions may or may not be silicided or part of the regions may be silicided depending on the options available in the CMOS flow. Note that the pocket implants are always the opposite type as the source/drain; namely, for a pMOS the pocket is donor type while the LDD and the source/drain are acceptor type. The triple well (p-well, n-well, and deep n-well) process allows more bipolar structures than the one shown in FIG. 4.
It is highly desirable to provide an improved bipolar transistor with graded base without added mask in CMOS flows